1. Field of the Invention
This invention is related to joining of semiconductor substrates. More specifically, the present invention provides an interconnect structure and method for joining or coupling together substrates employing transient liquid alloy bonding.
2. Description of the Prior Art
A patentability investigation was conducted and the following U.S. Patents were discovered: U.S. Pat. No. 5,334,804 to Love et al.; U.S. Pat. No. 5,374,344 to Gall et al.; U.S. Pat. No. 5,374,469 to Hino et al.; U.S. Pat. No. 5,384,690 to Davis et al.; U.S. Pat. No. 5,421,507 to David et al.; U.S. Pat. No. 5,432,998 to Galasco et al.; U.S. Pat. No. 5,509,196 to Davis et al.; U.S. Pat. No. 5,620,782 to Davis et al.; U.S. Pat. No. 5,736,679 to Kresge et al.; U.S. Pat. No. 5,376,403 to Capote et al.; U.S. Pat. No. 5,128,746 to Pennisi et al.; U.S. Pat. No. 5,232,532 to Hori; U.S. Pat. No. 5,157,828 to Coques et al.; U.S. Pat. No. 5,187,123 to Yoshida et al.; U.S. Pat. No. 5,839,188 to Pommer; and U.S. Pat. No. 5,842,273 to Schor.
U.S. Pat. No. 5,334,804 to Love et al. discloses an interconnect structure for connecting an integrated circuit (IC) chip to a supporting substrate. The supporting substrate serves to communicate signals between the IC chip and the xe2x80x9coutside world,xe2x80x9d such as other IC chips. In one embodiment, the interconnect structure is disclosed as comprising an interconnect substrate having a first post disposed on one of its surfaces and a second post disposed on another of its surfaces. One post is for contacting the IC chip and the other is for contacting the major substrate. Each post includes an elongated body having top and bottom ends, with the bottom end being mounted to one of the substrate surfaces and the top end having a substantially flat surface which is substantially co-planer with the substrate surface. The interconnect substrate of U.S. Pat. No. 5,334,804 to Love et al. further includes a device for de-concentrating the mechanical stain present at one or both of the top and bottom ends of each post. The first and second posts are electrically coupled to one another so that an electrical signal may pass from IC chip to the supporting substrate, and vice-versa.
U.S. Pat. No. 5,374,344 to Gall et al. discloses parallel processors, and more particularly, parallel processors having a plurality of printed circuit cards and/or boards, e.g., dedicated printed circuit cards and/or boards, for carrying processors, memory, and processor/memory elements. The printed circuit cards and/or boards are mounted on a plurality of circuitized flexible substrates, i.e., flex strips. The circuitized flexible substrates connect the separate printed circuit boards and cards through a relatively rigid central laminate portion. This central laminate portion provides means, e.g., Z-axis means, for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection and communication. U.S. Pat. No. 5,374,344 to Gall et al. also discloses parallel processor systems having a plurality of individual processors, e.g., microprocessors, and a plurality of memory modules. The processors and the memory can be arrayed in one of several interconnection topologies, e.g., an SIMD (single instruction/multiple data) or an MIMD (multiple instruction/multiple data).
U.S. Pat. No. 5,374,469 to Hino et al. discloses a flexible printed substrate imparted with an adhesive property for loading on an external substrate, a double printed substrate having formed on both surfaces thereof a metal layer or a wiring circuit. The flexible printed substrate comprises an insulating resin layer including a low-linear expansion polyimide resin layer and a thermoplastic polyimide resin layer, and a metal layer or a wiring circuit formed on the low-linear expansion polyimide resin layer of the insulating resin layer, wherein a mixed region of the polyimide resin components is formed in the interface between the low-linear expansion polyimide resin layer and the thermoplastic polyimide resin layer.
U.S. Pat. No. 5,421,507 to Davis et al. discloses a method of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form an eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au-Sn 20 wt % eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, multilayer, high performance circuit board is produced, electrically joined as selected lands by the solid alloy.
U.S. Pat. No. 5,432,998 to Galasco et al. discloses a method of laminating circuitized polymeric dielectric panels with pad to pad electrical connection between the panels. This pad to pad electrical connection is provided by a transient liquid phase formed bond of a joining metallurgy characterized by a non-eutectic stoichiometry composition of a eutectic forming system. The eutectic temperature of the system is below the first thermal transition of the polymeric dielectric, and the melting temperature of the joining metallurgy composition is above the first thermal transition temperature of the polymeric dielectric.
U.S. Pat. Nos. 5,384,690, 5,509,196 and 5,620,782, all to Davis et al. disclose a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is taught as being provided through a switch structure that is implemented in the laminate. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection and communication. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemically compatible with and bondable to the perfluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with and not bondable to the perfluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.
U.S. Pat. No. 5,736,679 to Kresge et al. discloses a through-hole interconnect for connecting a power plane conductor to a through-hole which includes a central pad connected to the through-hole and a deformable hinge that connects the central pad with the power plane conductor in a multilayer circuit board. The central pad and hinge are defined by a non-continuious area removed from the plane conductor. During a compression process to join the core assemblies, deformation of the hinge advantageously absorbs the shear forces and allows the power plane beyond the hinge to remain substantially planar. The resulting multilayer laminated circuit board includes a plurality of cores laminated together in a stacked configuration and a plurality of plated through-holes defined in the multilayer laminated circuit board, each of which is connected to a plane conductor by a hinge deformed so that the interconnect area is aligned outside of a plane defined by the plane conductor. U.S. Pat. No. 5,736,679 to Kresge et al. also discloses and teaches that the hinged interconnect avoids shearing problems and thereby improves the reliability of the connection between the through-hole and the power plane, increasing the manufacturing yield and reducing costs.
U.S. Pat. No. 5,376,403 to Capote et al. discloses electrically conductive compositions which contain metal and solder in addition to polymer forming constituents. A technique is described for eliminating voids in bonding a chip to a flexible substrate. A flexible pad or paper is connected to the underside of the flexible substrate, which will deform during bonding and allow air to flow out of the liquid adhesive before it cures and hardens. The adhesive used to bond the chip to the flexible substrate is liquid or paste (not bonding film or sheet) and the objective is air bubble elimination during bonding.
U.S. Pat. No. 5,128,746 to Pennisi et al. teaches a flux containing polymer forming composition. The flux forming constituent is disclosed as an acid selected from the group consisting of abietic acid, adipic acid, ascorbic acid acrylic and, citric acid, and malic acid.
U.S. Pat. No. 5,232,532 to Hori describes a technique for eliminating voids in bonding of a chip to a flexible substrate. The goal is to use flexible pad or paper underneath the flexible substrate, which will deform during bonding and allow air to flow out of the liquid adhesive before it cures and hardens.
U.S. Pat. No. 5,127,828 to Coques et al. describes use of an adhesive loop between a substrate and a support so that a partial vacuum may be applied to the space between the substrate and the support. The objective is to have uniform squeezing of adhesive and therefore uniform spacing between the substrate and the support after the adhesive is cured.
U.S. Pat. No. 5,187,123 to Yoshida et al. describes a void free adhesive layer in bonding of a semiconductor device to a lead frame. The main area of adhesive application is the back side of the die. There is no metal connection between the semiconductor device and the lead frame. The adhesive is applied in liquid or paste form in several pre-arranged spots, so as to prevent formation of voids during semiconductor device attachment onto a lead frame.
U.S. Pat. No. 5,839,188 to Pommer discloses the use of non-conductive particles (i.e., xe2x80x9cgaugexe2x80x9d particles) to provide a uniform gap or separation between two or more substrates, and the use of conductive pastes of copper post/tin to form an electrical interconnection.
U.S. Pat. No. 5,842,273 to Schor discloses the use of a conductive adhesive to from an electrical connection between substrates. The adhesive is an elastomeric thermoset with conductive particles, flakes, etc. No solder is used. Electrical connection is primarily through metal contact.
Conventional underfill process, such as that disclosed in the foregoing prior art, for flip chip to substrate joining is limited to very small joining areas (typically 1-inch by 1-inch area or less). Substrate buildup is expensive. As the requirements of high density substrates increase, a simple and reliable interconnection process is needed to fulfill this demand. For typical solder printing methods, there is a limitation on the size of solder bumps, and the yield will be low for fine-pitch small bumps. Furthermore, joints will be less reliable on micro-bumps. It is desirable to have an interconnect reliable process that may be easily down-sized to the dimension of HDI substrates. Therefore, what is needed and what has been invented is an economical method that can provide the foregoing requirements by employing an insertion structure and a transient liquid alloy bonding. What is also needed and what has been invented is a method for bonding or coupling together conductive structures through transient liquid alloy bonding.
The present invention provides a method for bonding conductive structures comprising compressing a thin layer of metal between one end of a conductive post and a conducting structure; transforming the thin layer of metal into a bonding layer having a melting temperature higher than the melting temperature of the thin layer of metal; and bonding the conductive post and the conducting structure together via the bonding layer. A dielectric material may be deposited around the conductive post. The thin layer of metal may comprise a material selected from the group consisting of In, Sn/Pb eutectic solder, Sn, Bi, and mixtures thereof. An electrically conductive article is formed. The electrically conductive article comprises the conductive post, the conductive structure, and the bonding layer disposed between the conductive structure and the conductive post. The bonding layer has a melting temperature substantially higher than a melting temperature of a bonding layer precursor which was disposed on an end of the conductive post and/or on the conductive structure and provided the genesis for the bonding layer.
Further aspects of embodiments of the present invention provide a method for producing an assembly of substrates comprising disposing a thin layer of metal on a conducting structure coupled to a first substantially planar substrate, and dispensing a liquid polymeric material between the conducting structure and a second substantially planar substrate which supports a conductive post. The liquid polymeric material is disposed inwardly from the edges of the first and the second substrate such that by pressing the liquid polymeric material between the first and the second substrates, the liquid polymeric material flows towards the edges of the first substrate and the second substrate. The method also includes compressing the thin layer of metal between an end of the conductive post and the conducting structure, transforming the thin layer of metal into a bonding layer having a melting temperature higher than the melting temperature of the thin layer of metal, and bonding the conductive post and the conducting structure together via the bonding layer. The method further also includes curing the liquid polymeric material. The liquid polymeric material comprises a polymer fluxing agent which may comprise a beta phenylacid and/or a beta phenylhydroxyacid. The beta phenylacid is selected from the group consisting of beta phenyacetic acid, beta phenylacetic acid, beta phenylacrylic acid, beta phenylcrotonic acid, and mixtures thereof. The liquid polymeric material preferably comprise from about 15% by weight to about 70% by weight of a polymeric resin, from about 15% by weight to about 70% by weight of a curing agent, and from about 0.10% by weight to about 20% by weight of a fluxing agent.
Embodiments of the present invention provide a method for producing an assembly of substrates comprising disposing a thin layer of metal on an end of a conductive post attached to a first substantially planar substrate, and dispensing a liquid polymeric material between a conducting structure on a second substantially planar substrate and the first substantially planar substrate. The liquid polymeric material is disposed inwardly from the edges of the first and the second substrates such that when the liquid polymeric material is compressed between the first and the second substrates, the liquid polymeric material flows towards the edges of the first and the second substrates. The method also comprises compressing the thin layer of metal between the end of the conductive post and the conducting structure, transforming the thin layer of metal into a bonding layer having a melting temperature higher than the melting temperature of the thin layer of metal, and bonding the conductive post and the conducting structure together via the bonding layer.
The present invention further provides a method for producing an assembly of substrates comprising dispensing a liquid polymeric material between a conducting surface, on a first substantially planar substrate and a conducting surface on a second substantially planar substrate. The liquid polymeric material is preferably disposed inwardly from the edges of the first substrate and the second substrate; The method further includes pressing the liquid polymeric material between the first substrate and the second substrate so that the liquid polymeric flows towards the edges of the first substrate and the second substrate; and curing the liquid polymeric material. The conducting surface on the first substrate is placed in contact with the conducting surface on the second substrate after pressing the liquid polymeric material between the first substrate and the second substrate. In another embodiment of the invention the liquid polymeric material is dispensed on dies present on the first or second substrate. Preferably at least one of the substrates has a planar surface area of at least 36 sq. inches, such as a dimension of from about 6 inches to about 6 inches.
The conducting surface of one of the planar substrates includes a solder bump which may or may not have a solder material fluxing agent. The liquid polymeric material comprises from about 15% by weight to about 70% by weight of a polymeric resin, from about 15% by weight to about 70% by weight of a curing agent, and from about 0.10% by weight to about 20% by weight of a polymer fluxing agent. The polymer fluxing agent comprises a beta phenylacid and/or a beta phenylhydroxyacid. The beta phenylacid is selected from the group consisting of beta phenylacetic acid, beta phenylacrylic acid, beta phenylcrotonic acid, and mixtures thereof.
The present invention also further provides a polymeric composition comprising from about 15% by weight to about 70% by weight of a polymeric resin, from about 15% by weight to about 70% by weight of a curing agent, and from about 0.10% by weight to about 20% by weight of a fluxing agent. The present invention also further provides an assembly of substrates comprising a lower substrate; a polymeric composition disposed on the lower substrate; and an upper substrate disposed on the polymeric composition which comprises from about 15% by weight to about 70% by weight of a polymeric resin, from about 15% by weight to about 70% by weight of a curing agent, and from about 0.10% by weight to about 20% by weight of a fluxing agent.
The present invention also further provides a method for forming an intermetallic region comprising depositing a dielectric layer on a circuitized layer having a conductive region; forming an aperture (e.g., by laser drilling) in the dielectric layer over the conductive region; and inserting a conductive body into the aperture, which produces a gap between a wall of the aperture and the conductive body. The conductive body comprises a main region and a depletion region which contacts the conductive region. The method further comprises forming an intermetallic region from the depletion region. The intermetallic region surrounds the sides and an end of the main region. The depletion region comprises tin and the main region comprises copper. The intermetallic region includes Cu3Sn. In a preferred embodiment of the invention, the circuitized layer is a first circuitized layer and the conductive body is disposed on a second circuitized layer. The method also further comprises laminating the first circuitized layer and the second circuitized layer together. The gap between the wall of the aperture and the conductive body is preferably filled with a dielectric material. The gap may be filled by laminating the dielectric layer.
The present invention yet al.so further provides a conductive article comprising a first circuitized layer having a dielectric layer and a first conductive region; and a second circuitized layer having a dielectric layer and a second conductive region. A via structure is disposed between the first and second conductive regions. The via structure preferably comprises a main region and an intermetallic region disposed around the sides and around one end of the main region.
These provisions together with the various ancillary provisions and features which will become apparent to those skilled in the art as the following description proceeds, are attained by the methods for joining and the high density interconnect structures of the present invention, preferred embodiments thereof being shown with reference to the accompanying drawings, by way of example only, wherein: